A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories, including read only memories (ROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). These memories have an array of individual memory devices, and an individual device in the array is also referred to as a cell. One array of devices is typically a subset of the entire memory. An EPROM is erased using ultraviolet light and an EEPROM is erased using an electrical signal. An electrical signal is used to write EPROMS and EEPROMS. In a conventional flash EEPROM ("flash" indicating all memory cells or sectors of cells are erased at once), memory cells are simultaneously erased to a low threshold voltage and then programmed, either individually or in small groups, to a high threshold voltage. EPROMs and EEPROMs are commonly used in data processing systems that require a nonvolatile memory that is reprogrammable.
A typical device structure for EEPROM cells is the floating-gate polysilicon transistor. A typical floating gate structure is illustrated in FIG. 1. As depicted in FIG. 1, a floating gate 10, sandwiched between two insulator layers 20 and 60, is between the substrate 30 and the ordinary select-gate electrode 40. The structure depicted in FIG. 1 is a stacked gate memory cell, the word "stacked" indicating that the floating gate 10 is stacked over the source 50 and drain 70 portions of the substrate. Another EPROM structure is a split gate structure wherein the portion of the floating gate only overlies the drain and no portion of the floating gate overlies the source. Split gate EPROM and EEPROM device structures are described in U.S. Pat. No. 5,349,220, to Hong which is hereby incorporated by reference. As a result, in EPROMS and EEPROMS, the select-gate voltage must be capacitively coupled in series with the floating gate rather than directly to the underlying channel.
There are n-channel and p-channel devices with the above structures. In the n-channel devices, the source and drain are doped with an n-type dopant and the substrate is doped with a p-type dopant. In p-channel devices, the source and drain contain p-type dopant and the substrate contains n-type dopant. In silicon based substrates, such as silicon or silicon germanium (SiGe) alloys, an example of a p-type dopant is boron and examples of suitable n-type dopants are arsenic and phosphorus.
EPROMS and EEPROMS are programmed by applying a set of bias voltages to the device depicted in FIG. 1. The voltage applied to the select-gate (hereinafter referred to as a control gate) is V.sub.C, the voltage applied to the drain is V.sub.D, and the voltage applied to the source is V.sub.S. The voltage applied to the substrate is referred to as V.sub.B and, typically, all cells in an array have the same V.sub.B applied thereto. Programming, as used herein, is the addition of negative charge to the floating gate.
Voltage differences, typically referred to as biases, between these various terminals are designated in the following manner: e.g., V.sub.CS =V.sub.C -V.sub.S etc. In n-channel devices writing biases are used to introduce additional negative charge onto the floating gate, thereby writing the cell. However, if the charged state is chosen as the "unwritten" state, introducing additional negative charge onto the floating gate will erase the cell. Bias conditions that are used to introduce a more negatively charged state are different from bias conditions that are used to read the charged state or to create a more positively charged state.
These write biases are typically a high control gate-to-source voltage (V.sub.CS) and/or a high drain-to-source voltage (V.sub.DS). These programming voltages are sufficient to cause a transfer of electrons from the bulk of the device (channel 80 and/or source 50 and/or drain 70) region to the floating gate 10 where they are trapped, thereby charging the floating gate more negatively. Charge is trapped in the floating gate 10 because the floating gate is isolated from the select-gate 40 by an insulating oxide layer 60 and from the drain-source-substrate region by another thin oxide insulating layer 20. The effect of trapping electrons on the floating gate is to raise the threshold voltage (V.sub.TH) to some predetermined level. Furthermore, these programming voltages are outside of the range of normal reading bias conditions so that an inadvertent write does not occur during reading.
EPROMS and EEPROMS typically include an array of floating-gate transistors. The V.sub.TH of a given cell can be determined by a sense amplifier when read and decoded into its logic value. For example, in a conventional two-state memory, a high V.sub.TH that is achieved by writing as described above is decoded as a logic one. In turn, the intrinsic V.sub.TH (the V.sub.TH of a device, which has not been written by adding negative charge to the floating gate 10) is decoded as a logic zero. Because the floating gate is isolated, the cell can remain programmed or erased for periods of up to 10 years and even longer.
However, certain problems are encountered when erasing and writing stacked-gate memory cells in arrays of memory devices configured in a common architecture known as a NOR array. A NOR architecture consists of a plurality of EPROM or EEPROM cells. In a NOR architecture, at least four cells are arranged such that there is a sequence of cells in two directions. The sequence of cells in the first direction are referred to as rows of cells and the sequence of cells in the second direction are referred to as columns of cells. A NOR array requires that there be at least two rows of cells and at least two columns of cells. Furthermore, in a NOR array, each column of cells has its own dedicated bit line and the drains of the cells in a given column are electrically connected to the same bit line. Still further, each row of cells has its own dedicated word line, and the gates of the cells in a given row are all electrically connected to the same word line. The sources are connected to a source voltage (V.sub.S) supply. In a NOR array, more than one bit line may be selected simultaneously, but only one word line is selected at a time.
The cells in the array are programmed and read individually. A cell is "selected" for programming or reading by applying certain voltages to the word line and the bit line that are connected to the selected cell. These voltages are different from the voltages applied to the remaining cells in the array. The remaining cells in the array are deselected. For example, a selected cell is typically read by applying voltages to the word and bit lines of the selected device. Specifically, a V.sub.CS that is greater than a desired V.sub.TH is applied to the word line and a V.sub.DS of about one (1) volt is applied to the bit line of the selected device. Voltages applied to the remaining word and bit lines in the array result in the application of a V.sub.CS =0 and a V.sub.DS =0 to the deselected devices. In the following, a V.sub.S =0 is assumed (but it is understood that V.sub.S can be greater than or equal to zero). When V.sub.S =0, V.sub.CS =V.sub.C (the voltage applied to the word line) and V.sub.DS =V.sub.D (the voltage applied to the bit line). Under such conditions, the selected cell(s) are read. In addition, under normal read conditions, V.sub.BS is equal to zero.
Prior to the introduction of charge onto the floating gates of the cells in a NOR sub-array of memory cells, all of cells in the sub-array are erased simultaneously. When a NOR array of memory cells is erased, the V.sub.TH distribution in the memory will be about 2 volts wide. This requires the erase to be carefully controlled to avoid "over-erasing" cells. A cell is over-erased when its V.sub.TH is less than zero. A cell with a V.sub.TH that is less than zero cannot be deselected during read. Such a cell cannot be left in this state because it adversely affects the operation of the array.
All cells in the programmed array must have a V.sub.TH that is sufficiently greater than zero to be deselected by application of a V.sub.CS equal to zero. As used herein, V.sub.TH represents the charge on the floating gate of a cell and so determines the state of the cell. The following describes how values of V.sub.TH are decoded as on or off by the sense amplifier. As used herein, V.sub.TH is the voltage of the device that determines whether the device is read as on or off by the sense amplifier.
V.sub.TH is defined here such that a sense amplifier connected to a bit line will read a device as on when V.sub.C is greater than or equal to the V.sub.TH of the device and V.sub.D is greater than to zero. A sense amplifier connected to a bit line will read a device as off when V.sub.C is less than the V.sub.TH of the device. Therefore, to the extent that cells are over-erased in a NOR array, those cells must be reprogrammed to a V.sub.TH greater than zero by a convergence technique. These over-erased cells cannot be written controllably using conventional channel hot electron injection techniques for introducing charge onto the floating gate because cells with a V.sub.TH less than zero contribute large bit-line leakage. Large bit-line leakage makes it difficult to supply the V.sub.DS required to write the cells. Furthermore, even if one or more of these over-erased cells are written, it is possible that deselected cells will be written in the process. Thus, the presence of over-erased cells disturbs the programming of the devices in the array.
Programming, as defined here, is the addition of negative charge to the floating gate such that the V.sub.TH of the cell increases. Erasure is the removal of negative charge from the floating gate such that the V.sub.TH of the cell decreases. Programming may be used to correct the over-erased state in which some of the cells have V.sub.TH .ltoreq.0 by programming all cells to some low V.sub.TH-TAR state that corresponds to the lowest logic state having the lowest V.sub.TH. Additional logic states may be programmed to higher values of V.sub.TH-TAR. For example, a conventional two state memory (logic 0 and logic 1) will have a V.sub.TH-TAR (0) and a V.sub.TH-TAR (1) such that 0&lt;V.sub.TH-TAR (0)&lt;V.sub.TH-TAR (1). The target threshold voltage for the erase step, V.sub.TH-TAR (erase), will be less than or equal to V.sub.TH-TAR (0); this choice will ensure that all cells are erased to or below the logic 0 state prior to any programming step. In the following, V.sub.TH-TAR is the target threshold for either the program or the erase cycle in which V.sub.TH is to either be increased to the V.sub.TH-TAR corresponding to any of the logic states or reduced to the erased threshold voltage, respectively.
Also, due to variations among individual devices, sense amplifier variations, uniformity of program convergence, changes in ambient temperature during programming, etc., it is desirable, and sometimes necessary, to verify that the NOR array has been correctly programmed or correctly erased. Such verification is often required to ensure that each device in the array has the desired amount of charge on the floating gate. However, the conditions used to verify the amount of charge on the floating gate of a selected device do not provide reliable information about the charge state of the selected device if there are over-erased cells in the array. If the read is not accurate, it is not known whether or not the device was programmed or erased properly. Accordingly methods for programming or erasing the floating gate of the EEPROM devices in NOR arrays which are less susceptible to errors caused by over-erased cells are desired. A method for programming floating gate EPROM and EEPROM devices in NOR arrays in which the charge on the floating gate can be verified more accurately is desired.